| 摘要 |
The output circuit comprises non-inverters(g1*,g2*) of transmission gates(T1,T2) and non-inverters(g3,g4) of transmission gates(T3,T4) for receiving an enable signal(ODE), inverters(g1,g2) of transmission gates(T1,T4) and non-inverters (g3*,g4*) of transmission gates(T3,T4) for receiving the enable signal (ODE) through an inverter(I1), a gate of p-MOS transistor(PM1) for receiving a sense AMP output(Dout) through the transmission gate(T2) and inverters(I4,I5), a gate of n-MOS transistor(NM1) for receiving the sense AMP output(Dout) through the transmission gate(T2) and inverters(I4,I5), and an output terminal connected with drains of the p-MOS and n-MOS transistors through a resistor(R), transmission gates(T3,T4) and inputs of inverters(I2,I4), thereby simplifying the circuit and reducing the delay time.
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