Improvements in and relating to integrated circuits

摘要

A thick copper interconnection structure and method for an LDMOS transistor for power semiconductor devices. A large LDMOS transistor is formed of a plurality of source and drain diffusion regions to be coupled together to form the source and drain (9). Gate regions (13) are formed between the alternating source and drain diffusions. Each diffusion region has a first metal layer stripe (17) formed over it and in electrical contact with it. A second metal layer conductor (21) is formed over a plurality of the first metal layer stripes, and selectively contacts the first metal layer stripes to form a source and a drain bus. A thick third metal layer (23) is then formed over each second metal layer bus, either physically contacting it or selectively electrically contacting it. The thick third level metal is fabricated of a highly conductive copper layer. The thick third level metal bus substantially lowers the resistance of the LDMOS transistor and further eliminates current debiasing and early failure location problems experienced with LDMOS transistors of the prior art. Other devices and methods are described.