Self-registered capacitor bottom plate local interconnect scheme for DRAM

摘要

A method and structure for a lower capacitor electrode (67) for a dynamic random access integrated (DRAM) circuit (50). A polysilicon gate layer (64) is formed over a thin layer of oxide (63) in a first region of a semiconductor substrate (49). Another oxide layer (62) is then formed overlying the polysilicon gate layer (64). A polysilicon layer (121) which was doped by S/D implant and includes the lower capacitor electrode (131) self-aligns and forms overlying a second region of the semiconductor substrate (100) and over the oxide layer (108) on the polysilicon gate layer (110). A nitride layer (127) forms on the lower capacitor electrode (131) portion overlying the second region. Exposed portions (132) of the polysilicon layer (121) are then oxidized. The S/D (114, 116) was formed by driving dopant from implanted second layer polysilicon (121). Portions of polysilicon (121) under the nitride layer (127) corresponding to the lower capacitor electrode (131) oxidizes at a slower rate than the exposed portions (132) of the polysilicon (121) giving rise to a birds beak structure. Such sequence of steps forms a self-aligned lower capacitor electrode (67) for a DRAM (50).