INDEXING AND MULTIPLEXING OF INTERLEAVED CACHE MEMORY ARRAYS

摘要

In a CPU (100), a cache memory array (610) for storing instructions and data is used. By employing interleaving of two logical memory arrays (459a and 459b), a high hit rate is achieved in the cache memory (424) to effectively reduce the number of accesses to slower main memory (not shown). Multiplexing circuits (e.g., 740) enable the array to be more densely packed and implemented with lower numbers of sense amplifiers.