FILTER FOR COMPUTER BUS SIGNALS

摘要

A circuit is described for processing an input signal received from a bus of a computer. The circuit includes level identification circuitry to characterize the magnitude of the input signal and to generate a corresponding level identification signal (50). Level toggle circuitry (54) is connected to the level identification circuitry to process the level identification signal and generate a level hold signal during spurious signal transitions in the input signal. The level toggle circuitry generates a level toggle signal at a predetermined point of the input signal after the spurius signal transitions have subsided. Level hold circuitry (52), connected to the level identification circuitry and the level toggle circuitry, processes the level identification signal, the level hold signal, and the level toggle signal. During spurious signal transitions in the input signal, the level hold circuitry maintains a high digital circuit output value in response to the level hold signal and the level identification signal. After the input signal has reached its peak value, a low digital circuit output signal is produced by the level hold circuitry in response to the level identification signal and the level toggle signal.