Semiconductor memory device having bit line equalizing means

摘要

A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.