发明名称 POWER SAVING CONTROL SYSTEM
摘要 <p>PURPOSE:To perform state transition control over respective CPUs and individual power saving control corresponding to the operation state so that the power consumption of a system in a stand-by state is suppressed without spoiling the consistency of the whole operation. CONSTITUTION:A multiprocessor system equipped with plural CPUs is provided with a processor bus monitor part 156 which detects the operation states of the individual CPUs by monitoring a processor bus and a system state monitor part 101 which monitors the load state of the system. Further, the system is provided with a system state control part 102 which controls the power consumption of the individual CPUs according to a report from the system state monitor part 101. If a state wherein the load on a specific CPU is small because of a key input waiting state continues, that is informed by the processor bus monitor part 156 to the system state control part 102, which sends a command to a clock switching part 153 to switch the clock supplied to the CPU to a low frequency.</p>
申请公布号 JPH086681(A) 申请公布日期 1996.01.12
申请号 JP19950079151 申请日期 1995.04.04
申请人 HITACHI LTD 发明人 HATTORI RYUICHI;SEKI YUKIHIRO;HIDA YASUHIRO;HARA ATSUSHI;OGURA TOSHIHIKO;OKAZAWA KOICHI;OEDA TAKASHI;SANO MAKOTO
分类号 G06F1/32;G06F1/04;G06F1/26;G06F9/50;G06F15/16;(IPC1-7):G06F1/26 主分类号 G06F1/32
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