| 摘要 |
A cache memory unit for use in a multiprocessor. The unit includes a data memory, a tag memory, a valid flag section, and an address bus, a comparator, and a clear signal producing section which produces a monitoring clear signal based on an output from the comparator and a monitoring strobe signal. The valid flag section receives the monitoring clear signal from the clear signal producing section. The cache memory unit further includes a monitoring strobe signal activating section which causes the monitoring strobe signal to be inputted to the clear signal producing section active or inactive whereby the valid flag section is cleared or prohibited from being cleared. The monitoring strobe signal activating section is reset when the operation enters into an in-circuit emulator (ICE) program and is set when the operation is freed from the ICE program. The cache memory unit enables the system to be debugged precisely without no delay in the execution of time. |
