| 摘要 |
PURPOSE:To make inter-network clock synchronization stable by increasing a gain with respect to a dominant input of a phase locked loop PLL circuit to be larger than the total sum of gains with respect to other inputs so as to eliminate out of synchronism. CONSTITUTION:In the configuration that a clock is supplied from an external board network to a mesh closed network comprising plural nodes, a subordinate synchronizing signal is given to an input terminal Ai of a node (i). in the stable state of a PLL circuit, inputs of a loop filter 23, that is, a total sum vi (t) of outputs of a phase comparator 21 are zero in all of nodes (i) and a timewise change in the vi (t) must be positive based on the principle of phase control of the PLL circuit. In order to satisfy the condition, an input phase component from the external network is increased larger than the total sum of other components to obtain a dominant input of a vector so as to make the phase table regardless of the input phase from an external broad network and the phase shift of its own link thereby eliminating out of synchronism. |
