BUFFER RAM CONTROLLER FOR INTERFACING VME BUS AND SUPPORTING DUAL PORT

摘要

The device is characterized in that a direction signal and an output enable signal of first to sixth buffers are applied to a buffer RAM controller in order to transmit data of a processor to the buffer RAM, in that the direction signal and the output enable signal of the second and third buffers are provided to data buffers to send the data of VME module to the buffer RAM, in that the direction signal and the output enable signal of the fourth and fifth buffers are applied to the data buffer by a DMA controller so as to send the data of the system bus to the buffer RAM, and in that the address transmission to the process, the VME module, and system bus, is performed in buffer RAM from the DMA controller.