发明名称 TEST CIRCUIT, SELF-TEST METHOD AND USUAL TEST METHOD
摘要 PURPOSE:To attain stable measurement even when an input clock signal having a redundant form is selected in the case of self-monitor by initializing again a synchronization detection circuit when the clock signal is selected and resetting an error counter. CONSTITUTION:A synchronization detection means 230 provides an output of a synchronization establish signal when a test pattern selected by a 1st signal selection means 210 is synchronized with an output pattern from a test signal confirmation means 220 and provides an output of an error signal when out of synchronism is taken. An error counter 240 counts error signals outputted from the synchronization detection means 230. Furthermore, an error counter re-start means 280 monitors a timing when a system of a clock signal received externally is switched and the circuit 230 is set initially within a switching time and when the switching of the system of the clock signal is finished, the counter 240 is reset. Thus, even when the switching of the system clock system takes place during the self-test, the usual test and the self-test are stably continued.
申请公布号 JPH07264267(A) 申请公布日期 1995.10.13
申请号 JP19940049489 申请日期 1994.03.18
申请人 FUJITSU LTD 发明人 MARUYAMA AKIRA;AIHARA KOJI
分类号 H03K21/40;G01R31/3193;H04L1/22;H04L7/00;H04L29/14;(IPC1-7):H04L29/14 主分类号 H03K21/40
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