发明名称 CLOCK GENERATION CIRCUIT
摘要 PURPOSE:To correct the error to be generated in the clock cycle for data processing by providing plural time signals TS by an image sensor 10. CONSTITUTION:A reference clock Sr which shows the reference time of a time signal TS is generated by a means 20 such as OR gate. The basic clock phiis counted by a frequency divider clock 30 till the generation and a frequency divider clock pN which divides it by a reference value counter 40 and then it is stored as a reference value S. After the generation of the reference clock Sr, the basic clock phi is given to an output counter 50 and an output clock phio is outputted whenever the prescribed number of it is accepted. The count value in the means 30 at the generation of the reference signal Sr is accumulated according to the output clock phio on an accumulation means 60. The count value of the basic clock phi till the generation of the output clock phio is set to the means 50 is made the reference value S at all times and when the accumulation value in the accumulation means 60 reaches N, it is set by the value with '1' added.
申请公布号 JPH07249984(A) 申请公布日期 1995.09.26
申请号 JP19940038926 申请日期 1994.03.10
申请人 FUJI ELECTRIC CO LTD 发明人 MORI KENICHI;YOKOYAMA SHOTARO
分类号 H04N1/19;H03K21/40;H03K23/64;H04N1/047;H04N5/06;(IPC1-7):H03K23/64 主分类号 H04N1/19
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