发明名称 |
Fault tolerant computer memory system with disablement feature. |
摘要 |
<p>In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.</p> |
申请公布号 |
EP0386461(B1) |
申请公布日期 |
1995.08.09 |
申请号 |
EP19900102078 |
申请日期 |
1990.02.02 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BLAKE, ROBERT MARTIN;BOSSEN, DOUGLAS CRAIG;CHEN, CHIN-LONG;FIFIELD, JOHN ATKINSON;KALTER, HOWARD LEO |
分类号 |
G06F12/16;G06F11/10;(IPC1-7):G06F11/00 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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