| 摘要 |
<p>PURPOSE:To suppress the variance of wiring lengths using a simple method by sorting all clock input nodes of function blocks into a finite number of groups based on a specific sorting method. CONSTITUTION:The flip-flops FF 3 are sorted into a finite number of groups based on such a sorting method that can decide that the density distributions are uniform in an area where the relevant group of FFs 3 is apparently included and also equal to each other. The FFs 3 existing close to each other in terms of space and belonging to the same group are gathered and grouped. For instance, the FFs 3 of an area 2 are sorted every four pieces into the FFs 4 of a 1st group, the FFs 5 of a 2nd group, and the FFs 6 of a 3rd group. So that an even FF density distribution is attained. One of clock buffers 7-9 is placed at the arithmetic average position of coordinates of the FFs 3 of each group. Then the output nodes of buffers 7-9 are wired individually to the clock input nodes of FFs 3 included in the corresponding group.</p> |
