CLOCK PHASE DETECTOR.

摘要

The invention relates to a clock phase detector for synchronous data transmission in the receiver of a data transmission system in which, in order to obtain a clock phase criterion from the received signal, two neighbouring main scanning values per symbol duration T and another intermediate scanning value midway between the two are formed. The pattern-dependent jitter is to be eliminated from such a clock phase detector. This is achieved by the invention by a modification to the Gardner process which eliminates the effects of neighbouring symbol interference on the clock phase criterion and thus reduces natural jitter.