| 摘要 |
The circuit is used for interface between CPU and a processor board for image compression and decompression. The interface circuit translates the TARGA or MMP data type to represent the true color image, into a data type for the compression board. The first interface module (21) converts the image data (D0-D5) into the pixel data (VD0-VD23). The second interface module (22) outputs the image data generated by converting the pixel data based on an external control signal (TARMD), data type, pixel enable signal (PIXOE0-PIXOE2), and a control signal.
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