| 摘要 |
<p>PURPOSE:To provide the microprocessor which is so constituted that the sampling time of a READY input signal is delayed furthermore. CONSTITUTION:In a microprocessor 1 which is provided with a CPU 2, a bus cycle control unit 3, and a clock generator 5 and samples an inputted READY signal 30 to control whether the bus cycle should be extended or not, the clock generator 5 generates a reference clock 35 and a clock having the n-fold frequency, and the bus cycle control unit 3 is provided with AND gates 9 to 12 taking the reference clock 35 and the n-fold clock as the input and latch means 7 and 8 taking the READY signal 30 as the data input, and outputs of AND gates 9 to 12 are inputted as the sampling clock to latch means 7 and 8.</p> |
