| 摘要 |
<p>PURPOSE:To enlarge the margin of a write recovery time. CONSTITUTION:A delay circuit 250 delays an inner write control signal by a prescribed time and supplys it to a global write driver GD. The global write driver is enabled in response to the delayed write control signal from the delay circuit and drive global write data busses GWD, the inverse of GWD in accordance with an inner write data from an input buffer. Block write driver BWD is enabled in response to the inner write control signal and a block selection signal and drives local write data busses LWD, the inverse of LWD in accordance with data on global write data busses. Write gate, WG connects bit lines bit, the inverse of bit to local data busses in response to a column selecting signal. Since output of block write driver is set at low level for a prescribed period of time by the delay circuit 250, precharge potentials of bit line is reduced and potential amplitude of bit line at the time of the data write is made small.</p> |
