| 摘要 |
PURPOSE:To inhibit the control of an equipment by a defective part by judging whether or not a storage element is a normal part or not, in a controller which controls the equipment. CONSTITUTION:When a signal RFSH (' ' indicates that the port is low active) of a CPU 10 is turned to 'L', bus drivers 16 and 23 are controlled by a control signal prepared by a control signal control circuit 21 based on the signal RFSH or the like, and a data outputting circuit 20f is connected with an address bus AB, and a control sub-bus SB is connected with a control bus CB. A CPU 20 outputs a prescribed address from the data outputting circuit 20f to the address bus AB, and reads an identification code preliminarily described in the prescribed address of a ROM 30 through a data bus DB and a latch circuit 25. The propriety of the read identification code is judged, and when it is judged to be improper, a signal P18 is set to 'L', and the CPU 10 is turned to a reset state. The CPU 20 repeatedly checks the ROM 30 while the CPU 10 is operated. |
