SEMICONDUCTOR MEMORY WITH METALLIC INTERCONNECTION LAYER OF THE SAME POTENTIAL AS THE WORD LINE AND CONNECTED THERETO OUTSIDE OF THE MEMORY CELL REGION

摘要

Memory cells (21), which serve as basic cells, are arranged in a matrix pattern. The memory cells (21) are each provided with a word line (W min ) which is integral with the gate electrode of a switch element (SW) and which is formed of polysilicon. A metallic interconnection layer (M) is arranged above the word line (W min ) and is applied with substantially the same potential as the word line (W min ). The metallic interconnection layer (M) and the word line (W min ) are connected together via through-holes (23A). The through-holes (23A) are formed in through-hole cells (23), which also serve as basic cells. The through-hole cells (23) and the memory cells (21) are arranged such that the number of rows of the former and the number of rows of the latter are in the ratio of one to at least two.