SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To improve a writing characteristic by arranging memory cells in a matrix shape at the intersection between a word line and a data line and adjusting the output voltage of a writing load circuit provided through a Y gate for selecting a data line so as to compensate the voltage drop due to the resistance component of the data line. CONSTITUTION:Memory cells M1-... for executing writing operation by injecting information charges into a floating gate are arranged in a matrix shape at the intersection between word lines W0-... and data lines D0-... so as to constitute a memory array. By receiving an address signal AX, a writing load circuit WA provided through Y gates Y0-... for executing selecting operation of data lines D0... recognizes the block in which a selected memory cell is provided. Corresponding to the block, a block decoder DE adjusts a variable resistor circuit VR and forms the output voltage for compensating a voltage drop due to the resistance component of the data line. Consequently, the writing characteristic of the memory cell is improved.