BURST TIME DIVISION MULTIPLEX INTERFACE FOR DATA LINK CONTROLLER

摘要

BURST TIME DIVISION MULTIPLEX INTERFACE FOR INTEGRATED DATA LINK CONTROLLER Subject burst time division multiplex interface connects circuits which perform "layer 1 (L1)" line control functions relative to a data communication network with devices which perform "Layer 2 (L2)" link control functions relative to the same network (L1 and L2 defined by OSI Specifications of the International Standards Organization). The interface is characterized by presentation of bursts of readiness indicating pulses from the L1 circuit to the L2 device during each basic time division multiplex time slot. The pulses indicate readiness of the circuits for data bit exchange, and separate time overlapped bursts are sent to indicate readiness of the circuit to send and receive data bits. Each burst contains a varied number of pulses ranging from O to n (where n is greater than 2, and in the disclosed embodiment equals 8). The bursts are positioned in a womdpw of time occupying a fraction of the slot interval close to the emd of each slot. This allows the L2 device to perform state swapping operations during the remainder of the slot to prepare for burst exchanges with different network channels to which the slots are allocatable ant to be able to devote maximum processing time to performance of L2 tasks required relative to the channels. The channels operate under various communication protocols (HDLC, LAP-D, clear/voice, etc.). Slot time spacings are variable by the L1 circuits to adjust to signalling conditions in the network.