| 摘要 |
A plurality of reference memory cell units are arranged to be connected to rows of matrix-patterned information memory cell units. Each of the reference memory cell units comprises a selection cell of an NMOS transistor, and three reference memory cells of depletion type NMOS transistors, and each of the information memory cell units comprises a selection cell of an NMOS transistor, and three information memory cells of NMOS transistors, one of which is of a depletion type. The selection cells are connected between the reference and information memory cells by a common selection line. The reference and information memory cells are connected by common word lines. Current mirror type sense amplifiers are connected to the columns of information memory cell units by digit lines. This arrangement avoids the occurrence of the unevenness of characteristics resulting from the fabrication process.
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