发明名称 Reduced capacitance lead frame for lead on chip package.
摘要 In a lead on chip, LOC, integrated circuit packaging arrangement (10), the conductors (46) terminate in fingers (50) that receive the bond wires (20). Adjacent the fingers (50), the conductors (46) have arm parts (52) extending over the major face of the integrated circuit (12). These arm parts (52) are formed by stamping, rolling or otherwise to present an upwardly opening channel with at least the bottom lateral margins (54, 56) of the arm part (52) raised above the plane of the bottom surface (58) of the arm part (52). This reduces sagging of the arm part (52) and capacitive interaction with the integrated circuit. <IMAGE>
申请公布号 EP0587112(A1) 申请公布日期 1994.03.16
申请号 EP19930114331 申请日期 1993.09.07
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 RUSSELL, ERNEST J.
分类号 H01L21/60;H01L23/495;H01L23/50 主分类号 H01L21/60
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