| 摘要 |
PURPOSE:To shorten a lock-up time and to reduce the quantity of jitter by measuring a phase difference between an input clock and a reproduced clock by a phase difference measuring circuit and controlling the quantity of clock insertion and deletion in accordance with the size of the measured value. CONSTITUTION:An edge detecting circuit 1 detects the leading edge of an input clock and a phase difference measuring circuit 2 measures a phase difference. A clock insertion/deletion control circuit 3 forms a clock insertion signal a4, a clock deletion signal a5, a clock insertion signal b6, and a clock deletion signal b7. Since insertion/deletion circuit a8 inserts/deletes a fine clock, i.e., a short period clock, and a clock insertion/deletion circuit b10 inserts/deletes a rough clock, i.e., a long period clock, follow-up is executed by the rough clock inserting and deleting signals b6, b7 when the phase difference is large and that is executed by the fine clock inserting and deleting signals a4, a5 when the phase difference is small. |
