| 摘要 |
PURPOSE:To easily perform accuracy check processing to evade an overflow trap or underflow trap in floating point addition/subtraction processing at high speed. CONSTITUTION:When an instruction fetched in a CPU 1 shows an FQADD instruction, an interruption inhibition signal 18 is outputted from a decoder circuit 11, and also, floating point addition processing is performed at a floating point adder 14, and the result is stored in the register T of a register file 12. When a computing error occurs, a computing error signal 19 is outputted, however, the gate of an AND circuit 15 is closed by the interruption inhibition signal 18, and the transmission of the signal 19 to an interruption generation circuit 16 is inhibited. The CPU 1 discriminates a type of computed result such as overflow, underflow, a positive value or negative value based on the content of the register T, and performs processing to set a corresponding bit pattern to a register R, and it is checked whether or not the type is the overflow or underflow by the pattern of the register R. |
