| 摘要 |
<p>A justifier (1) for performing the parallel justification of data onto a DS-3 mapping includes an input bus (2) for selectively communicating 8 respective I bits simultaneously to the justifier (1). An output bus (3) receives I, R, O and C bits from the justifier in accordance with the mapping at an eighth of the envelope rate of 44.736 Mb/s. A first data path (5) is connected to input bus (2) via a latch (6) for communicating to output bus (3), during a first cycle of the GCLK, a required number of the I bits. A second data path (7) is also connected to input bus (2) via the same latch (6) for communicating to output bus (3), over one or more subsequent GCLK cycles, the remainder of the I bits such that the mapping is satisfied. Justifier (1) also includes control means in the form of a control circuit (8) for regulating the flow of the I bits along the first and second paths (5,7). Circuit (8) is responsive to a first control signal provided by a sequencer which is indicative of the mapping to be followed. The I bits moving along the first and second data paths (5,7) are received by a triangular multiplexer (27) which selects an appropriate number of I bits from each path for subsequent transmission to bus (3). De-justifier (45) allows the de-justification of data from a predetermined mapping and is generally complementary in operation to justifier (1). Consequently, the de-justifier is ideally suited to the de-justification of data originating from justifier (1). <IMAGE></p> |
