| 摘要 |
A parallel processor comprising: an assembly (21) of alpha series of K elemental arithmetic units (UCEi,j), wherein each of the elemental arithmetic units (UCEi,j) has M data input lines (Lce) and N data output lines (Lcs), and each of said lines (Lce, Lcs) is connected to one of the input/output lines (Lces) of the assembly (21); a bulk memory (22) having O input/output lines (Lmes) for writing in and reading out words of O bits, said assembly (21) transferring data to and from said bulk memory; a transposing structure performing the "direct" conversion of a set of Q data items having P bits into P words having Q bits, said transposing structure further performing the "reciprocal" conversion of P' words having Q' bits into Q' data items having P' bits; and a set of ports (24) for transferring data to and from the assembly (21), the memory (22) and the transposing structure (23). Said processor may be used to perform repetitive processing, particularly image processing.
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