Method and apparatus for arbitrating access to a microprocessor having real and protected modes

摘要

A microprocessor access arbitration network which arbitrates among HOLD, RESET and REFRESH request commands by controlling a preempt bus so that a system memory refresh cycle is never delayed by a DMA or bus master operation is described. If a HOLD request is in progress for an operation other than a REFRESH cycle when a REFRESH cycle is initiated, that HOLD request is delayed while the REFRESH cycle proceeds to completion.