Flash memory and data processor.

摘要

Of a pair of memory cells Q21 and Q31 sharing the source S1 of the flash memory cell, only one of the paired memory cells is erased, and the other memory cell is then erased. Specifically, the memory cells on an even row A2 is erased, and the memory cells on an odd row A3 are then erased. An erasure preventing voltage is applied to the odd rows, while the even rows are being erased, and to the even rows while the odd rows are being erased. <IMAGE>