发明名称 SEMICONDUCTOR STORAGE INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To detect and save a data holding defect by outputting information whether errors are present in plural bits or not and information specifying the bit having an error when the errors are present in plural bits to the outside. CONSTITUTION:The presence of the error is detected by an error detection circuit 6 and when the error is present, at least one bit among error detection bits C1-C4 becomes 1. The error detection bits C1-C4 and data Drj are inputted to an error correction circuit 7 and it is decided that the error occurs in any bit of the data Drj. The level of the data Drj is inverted when the error is present and a DOj error-corrected is outputted. On the other hand, the negation data of all read data are outputted from a data output circuit 8 when only one '1' among the signals C1-C4 is outputted. When the error is present in data Dr1-Dr8, the data bits except one bit containing the error become the level that the level of original data is inverted and are outputted.</p>
申请公布号 JPH05217400(A) 申请公布日期 1993.08.27
申请号 JP19920000040 申请日期 1992.01.06
申请人 NEC CORP 发明人 KONDOU ICHIYOSHI
分类号 G11C17/00;G11C16/06;G11C29/00;G11C29/42;(IPC1-7):G11C29/00 主分类号 G11C17/00
代理机构 代理人
主权项
地址