| 摘要 |
<p>PURPOSE: To improve the jitter of a synchronous-asynchronous converter by numerically controlling the phase of a gap generator and, at the same time, continuously controlling the phase of an output clock. CONSTITUTION: A receiver/decoder 102 converts STM-1 data signals and clocks into digital signals having regular gaps and records the digital signals in an elastic memory as payload data. A gap generator 106, on the other hand, generates a clock signal having smooth GAP in response to a control signal GAPCTRL from a digital filter 105 and supplies the clock signal to the elastic memory 104 and the output of a synchronous-asynchronous conversion unit after removing a residual high-frequency jitter by supplying the clock signal to a phase-locked loop 106. Then the generator 103 tracks and controls an accumulated phase error by introducing a pulse or gap to an output clock generated in accordance with the instantaneous phase difference between the generated clock and a target clock. Therefore, the jitter of the conversion unit can be improved.</p> |
