CIRCUIT FOR CHECKING AND PREVENTING DATA CONSISTENCY IN PIPELINE PROCESSING

摘要

The circuit is for inputting and outputting correct data value in a processor using a 3 step pipe line. It includes 3 multiplexers (1,2,3) for receiving internal control input ?(RA-A,RA-B),(RB-A,RB-B),(RC-A,RC-B)?-00,10,01,11-through their A inputs and controlling outputs (A,W,B,C).