发明名称 PLL FREQUENCY SYNTHESIZER
摘要 PURPOSE:To reduce the transient response caused when an output frequency is selected, to converge the response at a high speed and to decrease noise in the vicinity of a carrier in the steady state by decreasing an open loop gain of an active filter at the frequency changeover. CONSTITUTION:A variable frequency divider 105 frequency-divides an output of a VCO 108 based on a frequency division signal inputted from a frequency division input terminal 101. A frequency phase comparator 106 compares an output of the frequency divider 105 with a reference signal inputted from a reference frequency input terminal 102 and outputs the result. An active loop filter 107 smooths an output of the frequency phase comparator 106 and selects the amplification factor based on a gain switching signal and amplifies the signal for the output. The VCO 108 outputs a signal with a frequency based on an output voltage of the filter 107.
申请公布号 JPH05183435(A) 申请公布日期 1993.07.23
申请号 JP19910359912 申请日期 1991.12.28
申请人 NEC CORP 发明人 NORIMATSU HIDEHIKO
分类号 H03L7/107;H03L7/18;H03L7/187 主分类号 H03L7/107
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