Output circuit of an integrated circuit having immunity to power source fluctuations

摘要

A series circuit of two P-channel transistors and a series circuit of two N-channel transistors are used respectively as a latch circuit which temporarily latches an input signal until the power source fluctuation caused by the change of the output signal is suppressed. The gates of the transistors of the two series-circuits are supplied with the output signal of an output-stage circuit and a delayed output signal obtained by delaying the above output signal so that either one of the two series-circuits can be controlled to be turned on so as to temporarily latch an input signal in a dynamic manner until the power source fluctuation is suppressed. Since the gate signals to the transistors of the two series-circuits are directly supplied without being passed through single-channel type transfer gates, a sufficiently large bias voltages are supplied to the gate of the latch circuits even under the low power source voltage. Thus, the output circuit capable of providing a desired operation characteristic even under the low operation voltage can be realized.