| 摘要 |
PURPOSE: To provide an input/output channel check and parity check detector in which a short pulse with less than 100ns can be detected and simultaneously glitch can be removed, and the exception of the synchronization and asynchronization report of input/output channel check and parity error can be detected. CONSTITUTION: An input/output channel check and parity check detector 90 includes two similar detection passes including check detectors 92 and 94, glitch removing circuits 96 and 107, and lead back registers 100 and 112. The channel check detector 92 receives the error signals of both parity error and channel check. The parity error detector 94 receives only the parity error signal. The check detectors 92 and 94 transmits the error signals to the glitch removing circuits 96 and 107, and the error signals are inputted to the lead back registers 100 and 112. A pulse with less than the minimum width is removed as a glitch. |
