| 摘要 |
A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis is disclosed. The microprocessor includes a phase locked loop 300 to generate clock signals for operations within the microprocessor PH2, PH1 and bus clock signals for data transfer operations on the bus CLKIN, CLKOUT. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses. Thus, during the manipulation of arithmetic operations which require multiple cycles to complete, the higher frequency of the core clock allows these types of operations to be complete in less time. therefore, reducing the time in which the bus is idle. <IMAGE>
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