发明名称 METHOD FOR IMPARTING TIMING SIGNAL TO PLURAL CIRCUIT BLOCKS
摘要 <p>PURPOSE:To save lobor and time for transmission delay measurement and delay quantity setting, and also, to improve the setting accuracy. CONSTITUTION:Two parallel running lines passing through near formed parts or installed parts of plural circuit blocks B1-Bn are laid on a substrate, a timing signal SA is applied to one end side PA of two parallel running lines, and also, to one line LA of two parallel running lines, and moreover, the same signal SB as the timing signal is applied to the other end side PB of two parallel tuning lines, and also, to the other line LB of two parallel running lines, the timing signal SA transmitted by one line LA from plural points P1-Pn on two parallel running lines and the timing signal SB transmitted by the other line LB are fetched, these pairs of signals SA1, SB1-SAn, and SBn are applied to each circuit block B1-Bn, and based on a time difference of every pair of signals, information related to an operation timing of each circuit block is reproduced. In this regard, C1-Cn denote reproducing means of the information related to the timing.</p>
申请公布号 JPH0566851(A) 申请公布日期 1993.03.19
申请号 JP19910229906 申请日期 1991.09.10
申请人 FUJITSU LTD 发明人 ASADA YOSHIMI
分类号 G06F1/10 主分类号 G06F1/10
代理机构 代理人
主权项
地址