| 摘要 |
PURPOSE:To improve yield and to reduce cost by providing a defective bit alternating means to detect the access of a defective by and to select an alternative bit. CONSTITUTION:When a select signal 20 is set in an L state, memory chips M0-M7 of a memory module 10 access an address designated by an address bus BA through a bit data line inputted to an I/O terminal. When a defective address equivalence circuit 14a detects the access of the defective bit, a selection control circuit 14c of a defective bit alternating means 14 turns the select signal 20 to the memory chips M0-M7 to an H state and supplies no signal. Then, the alternative address in a high-speed memory circuit 14b being a memory for defective bit alternate to compensate the defective bits of the memory chips M0-M7 is selected. On the other hand, when the address designated by the address bus BA is corresponding to the memory chips M0-M7 in the other case, the select signal 20 is supplied to the memory chips M0-M7. |
