发明名称 Method and apparatus for the inspection of patterns
摘要 The present invention relates to a technique, in the inspection of a defect of a semiconductor memory or the like, in which chip comparison is separated from repetitive pattern comparison in a region of a wafer to be inspected whereby both the comparisons are rendered possible to perform in parallel in one and the same scanning.
申请公布号 US5173719(A) 申请公布日期 1992.12.22
申请号 US19900630190 申请日期 1990.12.19
申请人 HITACHI, LTD.;HITACHI TOKYO ELECTRONICS CO., LTD. 发明人 TANIGUCHI, YUZO;FUKUI, TOORU;SAITO, MIKIHITO;HORI, YOSHIICHI;KAMAGATA, TAKAHIRO
分类号 H01L21/66;G01N21/93;G01N21/956 主分类号 H01L21/66
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