| 摘要 |
<p>PURPOSE: To provide a power control circuit for supplying a means in order to limit active power requested by a CMOS EPROM device. CONSTITUTION: An input circuit 11 is provided with a chip enable buffer 12 and plural input buffers, of which three input buffers are shown by 14, 16 and 18, and the respective buffers are connected to a microprocessor or a memory managing circuit. The outputs of the respective chip enable buffer and address buffers are respectively supplied to relational address transition detectors 20, 22, 24 and 26, these output signals are supplied to a power drop control circuit 30, on the other hand and the respective address buffers are supplied to a decoder. The outputs of respective address transition detectors are coupled by an OR gate 28 and its signal is inputted to a triple pulse sequencer 30. The triple pulse sequencer 30 generates a control signal for a system 10.</p> |
