| 摘要 |
<p>This multiprocessor circuit has interruption restriction circuits (21-24) connected between the interruption line (1) for inputting interruption signals and each of CPUs (11-14) connected in parallel with the interruption line (1) to restrict the input of interruption signals to each CPU under certain conditions. This interruption restriction circuit (21-24) counts the number of interruption signals received by each CPU during a specified period set at the timer using a counter means (32). When the count for a CPU exceeds the predetermined value, the multiprocessor circuit causes the input disabling means (33,34,40) to disable the input of interruption signals to that CPU for a certain period of time and thereby distributes the interruption signals to a plurality of CPUs almost equally. <IMAGE></p> |
