发明名称 ARITHMETIC PROCESSOR
摘要 PURPOSE:To prevent the lowering of operation speed when an arithmetic result is zero by providing a holding means which is set when the arithmetic result of an arithmetic means is not zero, and hold a set state until the operation of all digits is completed and executing the zero discrimination of the arithmetic result by referring to the holding means. CONSTITUTION:When subtraction is executed materially by decimal addition/ subtraction arithmetic processing and moreover the result of it is zero, it is necessary to modify the code of the result into a positive code and when the arithmetic result by an arithmetic means 1 is any number except zero every time when an operation is executed by an arithmetic means 1, the effect of it is accumulate-held by a holding means 2. Then, the holding means 2 is referred to at the end of the operation of all digits and the holding means 2 is not set, that is, all the digits are zero, the code is modified into the positive code. Thus, the subtraction is executed materially by the decimal addition/ subtraction arithmetic processing and moreover even when the result of it is zero, the lowering of operation speed is prevented.
申请公布号 JPH04191925(A) 申请公布日期 1992.07.10
申请号 JP19900324827 申请日期 1990.11.26
申请人 FUJITSU LTD 发明人 IKEDA MASAHIRO;SATO NOBUYOSHI
分类号 G06F7/50;G06F7/00;G06F7/493;G06F9/30 主分类号 G06F7/50
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