| 摘要 |
The latched accumulator fractional-N synthesiser has reduced residual error for use in digital radio transceivers. The divisor of the frequency divider (103) of the synthesiser is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched so that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, so that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109). |
