发明名称 |
METHOD OF MAKING SEMICONDUCTOR INTEGRATED CIRCUIT, PATTERN DETECTING METHOD, AND SYSTEM FOR SEMICONDUCTOR ALIGNMENT AND REDUCED STEPPING EXPOSURE FOR USE IN SAME |
摘要 |
According to the present invention, in making alignment between a semiconductor integrated circuit wafer and a mask or a reticle in light exposure of the wafer with a monochromatic light such as g-, i- or h- line of a mercury lamp, using a reduced stepping exposure system, light from a predetermined pattern on the wafer is taken out to an off-axis position and observed according to a through-the-lens method; in this case as a characteristic feature of the invention, the observation light is taken out from below the reticle and is passed through chromatic aberration correcting lenses, thereby permitting the use of a polychromatic or continuous spectrum light.
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申请公布号 |
US5094539(A) |
申请公布日期 |
1992.03.10 |
申请号 |
US19890313180 |
申请日期 |
1989.02.21 |
申请人 |
HITACHI, LTD. |
发明人 |
KOMORIYA, SUSUMU;KAWANABE, TAKAO;NAKAGAWA, SHINYA;OOSAKAYA, TAKAYOSHI;IRIKI, NOBUYUKI |
分类号 |
G03F9/00 |
主分类号 |
G03F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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