发明名称 BIT SYNCHRONIZATION CIRCUIT
摘要 PURPOSE:To ensure synchronization by dividing a modulation signal into I and Q components with a different phase, integrating them separately, obtaining a bit timing error and correcting the deviation of bit timing so as to make the error zero. CONSTITUTION:A PCM-PSK modulation signal is inputted to the circuit, shifted by a 90 deg. phase shifter 2 in both polarities by using a signal generated from a local oscillator 1 to obtain I and Q components whose phases differ by 180 deg.. Then the l and Q components are given to adders 9/11, digitized by A/D converters 7/8 respectively and the I and Q components are integrated for a bit timing period in a prescribed timing. Then a phase angle thetak of a modulation carrier obtained based on the sum output of the I and Q components is obtained by a tan computing element 17 to detect the presence of deviation of the bit timing. Moreover, a computing element 20 corrects the deviation of the bit timing so that the bit timing error obtained based on the phase angle thetak and the timing error of the I and Q components are made zero thereby securing the synchronization of the bit timing. Thus, the synchronization of the modulation carrier is not required and the synchronization is secured.
申请公布号 JPH03280759(A) 申请公布日期 1991.12.11
申请号 JP19900082657 申请日期 1990.03.29
申请人 NEC CORP 发明人 SAGAWA KAZUMI
分类号 H04L27/22;H04L7/00 主分类号 H04L27/22
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