| 摘要 |
<p>A high speed processor (HSP) including a processor interface, an output pipeline (212) interface, an input pipeline (214) interface, and a multichip floating point processor (110). The floating point processor (110) further comprises a data register (200) file memory, a coefficient register (204) file memory, a floating point multiplier-accumulator (201), a microsequencer (206) and a control store (208) random access memory (RAM). The high speed processor provided by the present invention is capable of operating at a clock rate of about 200MHz with the floating point processor capable of 400 MFLOPS peak performance. In one embodiment of the invention, the HSP is entirely self contained in a TFML package with all high speed interfaces residing on the package substrate and only C-MOS speed interfaces residing off of the FPP package. The FPP comprises five GaAs integrated circuit consisting of the floating point multiplier-accumulator (MACC), the plurality of multi-port register file memories (RFM), RAM for microprogram storage and a clock generator. <IMAGE></p> |
