| 摘要 |
A multi-chip, self-aligning, integrated circuit flip-chip assembly (300) using flexible connection assemblies (400) for its attachment is enclosed in an integrated circuit package (100). The connection assembly (400) contains connection pillars (376) which are attached to die (104) and carrier wafer (102) by means of flexible membranes (370) covering cavities (368). Each pillar consists of two opposing connection posts, (222) of die (104) and (216) of carrier wafer (102), joined by solder bump (228). A post is formed by etching a ring into the dielectric around predefined metal islands (342 or 226, 346, 348 and 350) provided by the process, which are interconnected by vias (354, 356 and 358) respectively to form conductive core (374). The conductive path established between first layer metal interconnects (342) and (226) via connection pillars (376) furnishes the electrical interface between chip and carrier in the flip chip arrangement. Flexure of the membranes allowed by the air filled cavities enables connection pillars (376) to tilt, so as to relieve the assembly of shear strain when subjected to differential thermal expansion. A membrane prober (500), using test metal bumps (582) in place of solder joints (228) but which is otherwise identical to flip-chip assembly (300), can be interfaced with a tester to perform conventional vector testing of individual chips (104) or complete multi-chip assemblies. Alternatively, test assemblies with metal bumps can be configured as "system-emulators" for testing individual production chips, by providing a test environment that accurately represents the full system. This test method dispenses with the many technical drawbacks and high costs associated with conventional vector testing, including the loading by the low tester impedance. |
