| 摘要 |
A phase-locked loop includes an oscillator controlled by means of a switching network and a microprocessor which generates, in response to the output of a phase detector, two groups of output signals. A first group (Q1 . . . QN) is for adjusting the frequency of the oscillator in steps by selectively switching in frequency determining elements, and a second group (P1 . . . PM) for feeding a pulse duration modulator. The pulse duration modulator produces a control signal for a frequency determining minimum element of the switching network. The control signal has a duty cycle indicative of the frequency determination contribution by the minimum element.
|
