| 摘要 |
<p>PURPOSE:To increase a read speed by discharging digit lines other than a digit line selected for the fall of a word line at the time of reading out a memory cell. CONSTITUTION:A digit line control circuit is provided which detects the word line selection of an X decoder and discharges non-selected precharged digit lines simultaneously with detection. Since a word line X1 and digit lines D2, D3 to Dm intersect each other in many positions in this case, many small parasitic capacities exist. Since these parasitic capacities have a very large value in total, the fall speed of a select signal X1 is increased by capacity coupling when non-selected digit lines are quickly discharged simultaneously with the fall of the select signal X1. Thus, the read speed of a transistor Q11 as the memory cell is increased.</p> |
